// Peripheral: FMC_Bank4_Periph  Flexible Memory Controller Bank4.
// Instances:
//  FMC_Bank4  mmap.FMC_Bank4_R_BASE
// Registers:
//  0x00 32  PCR4  PC Card  control register 4.
//  0x04 32  SR4   PC Card  FIFO status and interrupt register 4.
//  0x08 32  PMEM4 PC Card  Common memory space timing register 4.
//  0x0C 32  PATT4 PC Card  Attribute memory space timing register 4.
//  0x10 32  PIO4  PC Card  I/O space timing register 4.
// Import:
//  stm32/o/f303xe/mmap
package fmc

// DO NOT EDIT THIS FILE. GENERATED BY stm32xgen.

const (
	PWAITEN PCR4 = 0x01 << 1  //+ Wait feature enable bit.
	PBKEN   PCR4 = 0x01 << 2  //+ PC Card/NAND Flash memory bank enable bit.
	PTYP    PCR4 = 0x01 << 3  //+ Memory type.
	PWID    PCR4 = 0x03 << 4  //+ PWID[1:0] bits (NAND Flash databus width).
	ECCEN   PCR4 = 0x01 << 6  //+ ECC computation logic enable bit.
	TCLR    PCR4 = 0x0F << 9  //+ TCLR[3:0] bits (CLE to RE delay).
	TAR     PCR4 = 0x0F << 13 //+ TAR[3:0] bits (ALE to RE delay).
	ECCPS   PCR4 = 0x07 << 17 //+ ECCPS[2:0] bits (ECC page size).
)

const (
	PWAITENn = 1
	PBKENn   = 2
	PTYPn    = 3
	PWIDn    = 4
	ECCENn   = 6
	TCLRn    = 9
	TARn     = 13
	ECCPSn   = 17
)

const (
	IRS   SR4 = 0x01 << 0 //+ Interrupt Rising Edge status.
	ILS   SR4 = 0x01 << 1 //+ Interrupt Level status.
	IFS   SR4 = 0x01 << 2 //+ Interrupt Falling Edge status.
	IREN  SR4 = 0x01 << 3 //+ Interrupt Rising Edge detection Enable bit.
	ILEN  SR4 = 0x01 << 4 //+ Interrupt Level detection Enable bit.
	IFEN  SR4 = 0x01 << 5 //+ Interrupt Falling Edge detection Enable bit.
	FEMPT SR4 = 0x01 << 6 //+ FIFO empty.
)

const (
	IRSn   = 0
	ILSn   = 1
	IFSn   = 2
	IRENn  = 3
	ILENn  = 4
	IFENn  = 5
	FEMPTn = 6
)

const (
	MEMSET4  PMEM4 = 0xFF << 0  //+ MEMSET4[7:0] bits (Common memory 4 setup time).
	MEMWAIT4 PMEM4 = 0xFF << 8  //+ MEMWAIT4[7:0] bits (Common memory 4 wait time).
	MEMHOLD4 PMEM4 = 0xFF << 16 //+ MEMHOLD4[7:0] bits (Common memory 4 hold time).
	MEMHIZ4  PMEM4 = 0xFF << 24 //+ MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time).
)

const (
	MEMSET4n  = 0
	MEMWAIT4n = 8
	MEMHOLD4n = 16
	MEMHIZ4n  = 24
)

const (
	ATTSET4  PATT4 = 0xFF << 0  //+ ATTSET4[7:0] bits (Attribute memory 4 setup time).
	ATTWAIT4 PATT4 = 0xFF << 8  //+ ATTWAIT4[7:0] bits (Attribute memory 4 wait time).
	ATTHOLD4 PATT4 = 0xFF << 16 //+ ATTHOLD4[7:0] bits (Attribute memory 4 hold time).
	ATTHIZ4  PATT4 = 0xFF << 24 //+ ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time).
)

const (
	ATTSET4n  = 0
	ATTWAIT4n = 8
	ATTHOLD4n = 16
	ATTHIZ4n  = 24
)

const (
	IOSET4  PIO4 = 0xFF << 0  //+ IOSET4[7:0] bits (I/O 4 setup time).
	IOWAIT4 PIO4 = 0xFF << 8  //+ IOWAIT4[7:0] bits (I/O 4 wait time).
	IOHOLD4 PIO4 = 0xFF << 16 //+ IOHOLD4[7:0] bits (I/O 4 hold time).
	IOHIZ4  PIO4 = 0xFF << 24 //+ IOHIZ4[7:0] bits (I/O 4 databus HiZ time).
)

const (
	IOSET4n  = 0
	IOWAIT4n = 8
	IOHOLD4n = 16
	IOHIZ4n  = 24
)
